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[Embeded-SCM Develop] DE2_NIOS_HOST_MOUSE_VGA

Description: 利用该源代码可以实现在DE2的板子上进行USB画笔的实验-use of the source code can be achieved in the board Dictyophora USB brush on the experiment
Platform: | Size: 1024 | Author: 杨阿胡 | Hits:

[VHDL-FPGA-Verilog] Chapter6Sample

Description: 描述了使用FPGA接口PDIUSBD12开发USB接口的流程.-Describes the use of FPGA Interface USB interface PDIUSBD12 development flow.
Platform: | Size: 141312 | Author: 玄冰 | Hits:

[Other Embeded program] ip

Description: usart的verilog代码.rar 包括很多的FPGA ip 源码，可以直接应用 uart_vhdl.zip sl811usb包含源程序.rar mc8051_design.zip mcpu_1[1].05.zip minicpu.zip mmc_lark_original.zip -USART the Verilog code. rar, including many of the FPGA ip source, can be applied directly uart_vhdl.zipsl811usb contains the source code. rarmc8051_design.zipmcpu_1 [1] .05. zipminicpu.zipmmc_lark_original.zip
Platform: | Size: 5391360 | Author: 钟阳 | Hits:

[VHDL-FPGA-Verilog] usb_funct.tar

Description: Verilog语言描述的USB 2.0接口和新功能固件。-Verilog language description of the USB 2.0 interface and new features in firmware.
Platform: | Size: 198656 | Author: 陈楚龙 | Hits:

[USB develop] usb_funct

Description: usb2.0的Verilog源代码,包含完整的源代码,没有测试激励文件-USB2.0 the Verilog source code, including complete source code, there is no incentive to test document
Platform: | Size: 212992 | Author: 高杰 | Hits:

[VHDL-FPGA-Verilog] detect

Description: 一个序列检测器的设计。程序不是问题，关键是理解状态机的编程思想。-A sequence detector design. Procedure is not a problem, the key is to understand the thinking of state machine programming.
Platform: | Size: 1024 | Author: chengpan | Hits:

[VHDL-FPGA-Verilog] USB_jtag

Description: 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机。-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine.
Platform: | Size: 1571840 | Author: 霍飘摇 | Hits:

[Graph Recognize] lcd-code

Description: 比较完整的LCD接口代码，verilog编写，分为6800和8080两种CPU接口，且有完整的仿真程序-Relatively complete LCD interface code, verilog prepared 6800 and 8080 is divided into two types of CPU interfaces, and there is a complete simulation program
Platform: | Size: 1831936 | Author: 李佳 | Hits:

[USB develop] USBipcore

Description: usb1.1 ip核，使用verilog编写-usb1.1 ip nuclear, prepared using the Verilog
Platform: | Size: 155648 | Author: liu | Hits:

[VHDL-FPGA-Verilog] usb11

Description: 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。-Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
Platform: | Size: 414720 | Author: 戴求淼 | Hits:

[VHDL-FPGA-Verilog] can

Description: 基于Verilog HDL 的一个CAN总线IP核。-Based on Verilog HDL a CAN bus IP core.
Platform: | Size: 89088 | Author: 戴求淼 | Hits:

[Embeded-SCM Develop] c51

Description: 51单片机，USB，触摸，TFT,的等综合应用，高级别。（usb+flash+touch+tft+ram综合测试）-51 single-chip, USB, Touch, TFT, integrated applications (usb+ flash+ touch+ tft+ ram General Test)
Platform: | Size: 1505280 | Author: 程明 | Hits:

[Applications] Asynchronous_slavefifo_wr

Description: usb-cy7c68013异步写传输代码verilog-usb-cy7c68013 asynchronous transfer write verilog code
Platform: | Size: 2048 | Author: 罗玉明 | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV

Description: --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.--------------------Verilog---------------- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
Platform: | Size: 168960 | Author: Sami | Hits:

[USB develop] USBtoUART

Description: USB转串口资料,相关USB芯片介绍、程序等-USBtoUART.rar
Platform: | Size: 691200 | Author: randy | Hits:

[VHDL-FPGA-Verilog] cp_uart_6

Description: 用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信 包括CP2102的配置 驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
Platform: | Size: 1024 | Author: vicky | Hits:

[VHDL-FPGA-Verilog] uart_tx_rx

Description: 该工程用verilog编写，已通过串口调试助手调试通过，接收模块采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。-Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complete the voluntary self-close feature.
Platform: | Size: 1312768 | Author: eric | Hits:

[Other] 68013

Description: 介绍了此控制器与FPGA接口的控制和HDL (硬件描述语言)实现方法。利用CY7C68013控制器的 Slave F IFO从机方式,用Verilog HDL在FPGA中产生相应的控制信号,实现对数据的快速读写。试验 结果表明此方案传输速度快、数据准确,可扩展到其他需要通过USB进行快速数据传输的系统中-This paper describes the controller and the FPGA interface to control and HDL (hardware description language) implementations. Use CY7C68013 controller Slave F IFO slave mode, using Verilog HDL in the FPGA generate a corresponding control signal to achieve fast read and write data. The results show that this program transmission speed, accurate data can be expanded to other needs through the USB for fast data transfer system
Platform: | Size: 365568 | Author: 余岳衡 | Hits:

[VHDL-FPGA-Verilog] WORKS

Description: Project of Adquisition Data, show in VGA and send to usb host
Platform: | Size: 9917440 | Author: lagartojj | Hits:

[VHDL-FPGA-Verilog] xtp051_sp601_schematics

Description: Xilinx公司最新的Spartan 6系列FPGA所用的开发板电路图，详尽包括了电源、IO、外设、USB等部分的内容，极具有参考价值，另外还有一个USB芯片 68013所使用的HEX文件可供下载-Xilinx' s new Spartan 6 Series FPGA development board used in circuit detail, including the power, IO, peripherals, USB and some other content, most with a reference value, in addition to a USB chip, 68013 using HEX file available for download
Platform: | Size: 311296 | Author: Frank | Hits:
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